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EM620FU16 series low power, 128kx16 sram 1 merging memory & logic solutions inc. merging memory & logic solutions inc. document title 128k x16 bit super low power and low voltage full cmos static ram revision history revision no. history draft date remark 0.0 initial draft december 18, 2002 0.1 2?nd draft add pb-free part number february 13 , 2004 emerging memory & logic solutions inc. it venture tower eastside 11f, 78, karac-dong, songpa-ku, seoul, rep.of korea zip code : 138-160 tel : +82-2-2142-1759~1766 fax : +82-2-2142-1769 / homepage : www.emlsi.com the attached datasheets are provided by emlsi reserve the right to change the specifications and products. emlsi will answer to your questions about device. if you have any questions, please contact the emlsi office.
EM620FU16 series low power, 128kx16 sram 2 merging memory & logic solutions inc. merging memory & logic solutions inc. 1 2 3 4 5 6 a lb oe a 0 a 1 a 2 cs 2 b i/o 9 ub a 3 a 4 cs 1 i/o 1 c i/o 10 i/o 11 a 5 a 6 i/o 2 i/o 3 d v ss i/o 12 dnu a 7 i/o 4 v cc e v cc i/o 13 dnu a 16 i/o 5 v ss f i/o 15 i/o 14 a 14 a 15 i/o 6 i/o 7 g i/o 16 dnu a 12 a 13 we i/o 8 h dnu a 8 a 9 a 10 a 11 dnu features ? process technology : 0.18 m m full cmos ? organization :128k x 16 bit ? power supply voltage : 2.7v ~ 3.3v ? low data retention voltage : 1.5v(min.) ? three state output and ttl compatible ? package type : 48-fpbga 6.0x7.0 general description the EM620FU16 families are fabricated by emlsi?s advanced full cmos process technology. the families support industrial temperature range and chip scale package for user flexibility of system design. the fami- lies also supports low data retention voltage for battery back-up operation with low data retention current. product family product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , typ.) operating (i cc1 .max.) EM620FU16 industrial (-40 ~ 85 o c) 2.7v~3.3v 55 1) /70ns 1 m a 2 ma 48-fpbga name function name function cs 1 ,cs 2 chip select inputs vcc power supply oe output enable input vss ground we write enable input ub upper byte (i/o 9~16 ) a 0 ~a 16 address inputs lb lower byte (i/o 1~8 ) i/o 1 ~i/o 16 data inputs/outputs dnu do not use r o w s e l e c t i/o circuit column select data cont data cont pre-charge circuit memory array 1024 x 2048 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 0 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 we oe ub lb cs 1 cs 2 i/o1 ~ i/o8 i/o9 ~ i/o16 v cc v ss control logic functional block diagram 1. the parameter is measured with 30pf test load. pin description 48-fpbga : top view (ball down)
EM620FU16 series low power, 128kx16 sram 3 merging memory & logic solutions inc. merging memory & logic solutions inc. absolute maximum ratings * * stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to vcc+0.3 (max. 4.0v) v voltage on vcc supply relative to vss v cc -0.2 to 4.0v v power dissipation p d 1.0 w operating temperature t a -40 to 85 o c functional description note: x means don?t care. (must be low or high state) cs 1 cs 2 oe we lb ub i/o 1-8 i/o 9-16 mode power h x x x x x high-z high-z deselected stand by x l x x x x high-z high-z deselected stand by x x x x h h high-z high-z deselected stand by l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active l h l h l h data out high-z lower byte read active l h l h h l high-z data out upper byte read active l h l h l l data out data out word read active l h x l l h data in high-z lower byte write active l h x l h l high-z data in upper byte write active l h x l l l data in data in word write active
EM620FU16 series low power, 128kx16 sram 4 merging memory & logic solutions inc. merging memory & logic solutions inc. dc and operating characteristics parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il or lb = ub =v ih v io =v ss to v cc -1 - 1 m a operating power supply i cc i io =0ma, cs 1 =v il , cs 2 = we =v ih , v in =v ih or v il - - 2 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 1 < 0.2v, lb < 0.2v or/and ub < 0.2v, cs 2 > v cc -0.2v, v in < 0.2v or v in > v cc -0.2v - - 2 ma i cc2 cycle time = min, i io =0ma, 100% duty, cs 1 =v il , cs 2 =v ih, lb =v il or/and ub =v il , v in =v il or v ih 55ns - - 23 ma 70ns - - 18 output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.2 - - v standby current (ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs=v ih or v il - - 0.3 ma standby current (cmos) i sb1 cs 1 > v cc -0.2v, cs 2 > v cc -0.2v ( cs 1 controlled) or 0v < cs 2 < 0.2v (cs 2 controlled), other inputs = 0~v cc (typ. condition : v cc =3.0v @ 25 o c) (max. condition : v cc =3.3v @ 85 o c) ll lf - 1 5 m a recommended dc operating conditions 1) 1. ta= -40 to 85 o c, otherwise specified 2. overshoot: v cc +2.0 v in case of pulse width < 20ns 3. undershoot: -2.0 v in case of pulse width < 20ns 4. overshoot and undershoot are sampled, not 100% tested . parameter symbol min typ max unit supply voltage v cc 2.7 3.0 3.3 v ground v ss 0 0 0 v input high voltage v ih 2.0 - v cc + 0.2 2) v input low voltage v il -0.2 3) - 0.6 v capacitance 1) (f =1mhz, t a =25 o c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/ouput capacitance c io v io =0v - 10 pf
EM620FU16 series low power, 128kx16 sram 5 merging memory & logic solutions inc. merging memory & logic solutions inc. parameter symbol 55ns 70ns unit min max min max read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co1, t co2 - 55 - 70 ns output enable to valid output t oe - 30 - 35 ns ub , lb acess time t ba 55 70 ns chip select to low-z output t lz1, t lz2 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz1, t hz2 0 20 0 25 ns ub , lb disable to high-z output t bhz 0 20 0 25 ns output disable to high-z output t ohz 0 20 0 25 ns output hold from address change t oh 15 - 15 - ns parameter symbol 55ns 70ns unit min max min max write cycle time t wc 55 - 70 - ns chip select to end of write t cw1, t cw2 45 - 60 - ns address setup time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns ub , lb valid to end of write t bw 45 - 60 - ns write pulse width t wp 45 - 55 - ns write recovery time t wr 0 - 0 - ns write to ouput high-z t whz 0 20 0 25 ns data to write time overlap t dw 25 30 ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns read cycle (v cc =2.7 to 3.3v, gnd = 0v, t a = -40 o c to +85 o c) write cycle (v cc =2.7 to 3.3v, gnd = 0v, t a = -40 o c to +85 o c) ac operating conditions test conditions ( test load and test input/output reference) input pulse level : 0.4 to 2.2v input rise and fall time : 5ns input and output reference voltage : 1.5v output load (see right) : cl = 100pf+ 1 ttl cl 1) = 30pf + 1 ttl 1. including scope and jig capacitance 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.8v cl 1) v tm 3) r 1 2) r 2 2)
EM620FU16 series low power, 128kx16 sram 6 merging memory & logic solutions inc. merging memory & logic solutions inc. t rc address cs1 cs2 ub , lb oe data out t co t oh t ba t oe high-z t bhz t ohz timing waveform of read cycle(2) ( we = v ih ) data valid t olz t blz t lz t aa t hz t rc address t aa data valid t oh previous data valid timing waveform of read cycle(1). (address controlled, cs 1= oe =v il , cs2= we =v ih, ub or/and lb = v il ) data out timing diagrams notes (read cycle) 1. t hz and t ohz are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection.
EM620FU16 series low power, 128kx16 sram 7 merging memory & logic solutions inc. merging memory & logic solutions inc. t wr (4) t wc address cs1 cs2 ub , lb we data in data out t cw (2) t aw t bw t wp (1) t as (3) high-z t dw t dh high-z t ow t whz data undefined timing waveform of write cycle(1) ( we controlled) data valid t wc address cs1 cs2 ub , lb we data in data out t cw (2) t wr (4) t aw t bw t wp (1) t dw t dh timing waveform of write cycle(2) ( cs1 controlled) tas(3) high-z high-z data valid
EM620FU16 series low power, 128kx16 sram 8 merging memory & logic solutions inc. merging memory & logic solutions inc. t wc address cs1 cs2 ub , lb we data in data out t cw (2) t wr (4) t aw t bw t wp (1) t dw t dh timing waveform of write cycle(3) ( ub , lb controlled) high-z high-z data valid t as (3) notes (write cycle) 1. a write occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs 1 or we going high.
EM620FU16 series low power, 128kx16 sram 9 merging memory & logic solutions inc. merging memory & logic solutions inc. data retention characteristics notes 1. see the i sb1 measurement condition of datasheet page 4. parameter symbol test condition min typ max unit v cc for data retention v dr i sb1 test condition (chip disabled) 1) 1.5 - 3.3 v data retention current i dr v cc =1.5v, i sb1 test condition (chip disabled) 1) - 0.5 - m a chip deselect to data retention time t sdr see data retention wave form 0 - - ns operation recovery time t rdr t rc - - t sdr t rdr data retention mode cs 1 > vcc-0.2v v cc 2.7v 2.2v v dr cs 1 gnd t sdr t rdr data retention mode v cc 2.7v cs 2 v dr 0.4v gnd cs 2 < 0.2v data retention wave form
EM620FU16 series low power, 128kx16 sram 10 merging memory & logic solutions inc. merging memory & logic solutions inc. 0 . 5 #a1 a 0 . 7 9 t y p . 0 . 2 5 t y p . e 2 0 . 2 6 e 1 e a b c d e f g h 6 5 4 3 2 1 b b1 0.5 c c 1 b/2 c 1 / 2 b c package dimension 48 ball fine pitch bga (0.75mm ball pitch) bottom view top view c d y min typ max a - 0.75 - b 5.93 6.00 6.03 b1 - 3.75 - c 6.93 7.00 7.03 c1 - 5.25 - d 0.30 0.35 0.40 e 1.00 1.04 1.10 e1 - 0.79 - e2 - 0.25 - y - - 0.08 notes. 1. bump counts : 48(8row x 6column) 2. bump pitch : (x,y)=(0.75x0.75) (typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity : 0.08(max) side view detail a a1 index mark unit: millimeters
EM620FU16 series low power, 128kx16 sram 11 merging memory & logic solutions inc. merging memory & logic solutions inc. em x xx x x x xx x x - xx xx memory function guide 1. emlsi memory 2. device type 3. density 5. technology 6. operating voltage 8. version 9. packages 10. speed 7. orgainzation 1. memory component 2. device type 6 ------------------------ low power sram 7 ------------------------ stram 3. density 1 ------------------------- 1m 2 ------------------------- 2m 4 ------------------------- 4m 8 ------------------------- 8m 16 ----------------------- 16m 32 ----------------------- 32m 64 ----------------------- 64m 4. option 0 ----------------------- dual cs 1 ----------------------- single cs 5. technology blank ------------------ cmos f ------------------------ full cmos 6. operating voltage blank ------------------- 5v v ------------------------- 3.3v u ------------------------- 3.0v s ------------------------- 2.5v r ------------------------- 2.0v p ------------------------- 1.8v 7. orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 8. version blank ----------------- mother die a ----------------------- first revision b ----------------------- second revision c ----------------------- third revision d ----------------------- fourth revision 9. package blank ---------------------- package w --------------------- wafer 10. speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. power ll ---------------------- low low power lf ---------------------- low low power(pb-free) l ---------------------- low power s ---------------------- standard power 4. option 11. power

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